In the first place, a general process for manufacturing a MOS type integrated circuit, and more specifically, a process for manufacturing a CMOS-type integrated circuit will be explained with reference to FIGS. 22A-22E.
As shown in FIG. 22A, a device isolation insulating film 102, an n-well 103 and a p-well 104 are first formed in a silicon substrate 101.
Then, as shown in FIG. 22B, after a gate insulating film 105 is formed, a polycrystalline silicon film is deposited over the entire surface. Subsequently, the resultant structure is processed by optical lithography and anisotropic etching to form a gate electrode.
In general, the polycrystalline silicon film thus formed is constituted of columnar polycrystalline silicon having an average grain diameter of several tens nm, as viewed from above. In such a columnar polycrystalline silicon film, numerous small crystal grains are present at the interface with the gate oxide film 105, as shown in FIG. 22C. The sizes of the crystal grains increase as they go away from the interface.
As shown in FIG. 22D, to prevent an electric field from being converged at an edge of the gate electrode 106, a post-oxidation film 107 is formed. Furthermore, impurity ions are doped at a level on the order of 1xc3x971013-1014/cm2 in the surface of the silicon substrate 101 by means of ion implantation. In this case, As+ or P+ is doped in an nMOSFET region and B+ or BF2+ is doped in a pMOSFET region. In this manner, a so-called LDD region 108 (recently, sometimes called an xe2x80x9cextension regionxe2x80x9d) is formed.
Then, as shown in FIG. 22E, a silicon nitride film or a silicon oxide film is deposited over the entire surface by a CVD method. The resultant structure is etch-backed to form a side-wall insulating film 109 on a side wall of the gate electrode 106.
Furthermore, As+ or P+ is doped in the nMOSFET region and B+ or BF2+ is doped in the pMOSFET region at a level on the order of 1015/cm2. After doped simultaneously in a source/drain region 110 and the gate electrode 106 as mentioned above, the impurity ions are electrically activated by high-temperature annealing such as RTA (Rapid Thermal Anneal).
Furthermore, for example, a CoSi2 film 111 is formed on the source/drain region 110 and the gate electrode 106 to reduce resistance of the source/drain region 110 and the gate electrode 106.
Thereafter, the resultant structure is subjected to usually-performed processes including an interlayer insulating film formation step, a metal wiring formation step, and a passivation film formation step. In this way, an LSI (not shown) is accomplished.
However, in the case where high integration and high performance of LSI are attained by using the aforementioned conventional techniques, the following problems are arisen.
The high integration and high performance of LSI are basically attained by reducing a gate channel length. However, it is not preferable to merely reduce the gate channel length since distribution of the electric field within the MOSFET is significantly changed, causing significant reduction in threshold voltage (short channel effect) and a reduction in punch-through voltage between the source and drain.
Accordingly, in practice, as the gate channel length is reduced, the gate insulating film and the depth of source/drain junction must be reduced in order to distribute the electric field almost uniformly within the MOSFET.
The source/drain junction depth can be generally reduced by suppressing the projection range by reducing the acceleration energy during the ion implantation and by performing the post annealing for a necessary and minimum time period. Since the impurity ions must be activated, a high-temperature/short-time annealing method, RTA, is generally performed after the ion implantation step. However, the junction depth has been shallower in recent years. In accordance with this tendency, the temperature and time of RTA have been reduced.
In these circumstances, a depletion phenomenon of the gate electrode has lately become a great matter of concern. The depletion phenomenon takes place when an energy band is bent at the interface between the gate electrode and the gate oxidation film and thereby a depletion layer is elongated (depletion). The depletion of the gate electrode is a phenomenon remarkably occurring when a density of electrically active impurity ions contained in the gate electrode near the interface with the gate oxidation film is low.
The depletion of the gate electrode is equivalent of reducing an effective capacitance of the gate oxide film, in other words, equivalent of increasing an effective film thickness of the gate oxide film.
The driving force for MOSFET can be expressed by a product of an activated carrier concentration and a carrier velocity. The activated carrier concentration is determined depending upon the effective capacitance of the gate oxidation film. Therefore, if the gate depletion occurs, the activated carrier concentration decreases. This directly means that the MOSFET driving force decreases.
The depletion of the gate electrode often and easily takes place when the gate electrode is formed of columnar polycrystalline silicon film and impurity ions are doped in the source/drain region and the gate electrode. This is because the impurity ions of the gate electrode are insufficiently activated since the annealing is performed at lower-temperature for shorter time, as the junction depth is reduced.
The reason why the impurity ions of the gate electrode are insufficiently activated, is as follows. Since the gate electrode is formed of the polycrystalline silicon film, grain boundaries are present in the gate electrode. The impurity ions of the gate electrode are usually segregated and inactivated in the grain boundary. The segregation/inactivation occurs more significantly as the temperature decreases. As a result, the impurity ions in the gate electrode are insufficiently activated as the temperature and time for the annealing are decreased, compared to that in the source/drain region.
Besides a lower activation rate at a certain temperature, there are another problem in that if later subjected to a step performed at 600 to 800xc2x0 C. (e.g., interlayer insulating film deposition step), impurity ions once activated in the crystal grains are diffused to the grain boundary and then segregated and inactivated.
In fact, it has been experimentally confirmed that the depletion rate significantly changes when the gate electrode taken after completion of the interlayer film deposition step is compared to that taken after completion of the final step, as shown in FIG. 23.
The segregation/inactivation readily occurs as the crystal grain is reduced in diameter and the grain boundary increased in number. Therefore, in the case, for example, a conventional case, where the columnar polycrystalline silicon film is used as the gate electrode, the number of the grain boundary increases near the interface between the gate electrode and the gate oxide film. As a result, in particular, the aforementioned segregation/inactivation problem easily occurs.
As is clear from the foregoing discussion, to solve the inactivation problem of impurity ions present in the gate electrode, it is better to increase the diameters of the crystal grains constituting the gate electrode (polycrystalline silicon film) because the grain boundary in the gate electrode reduces. However, the use of the polycrystalline silicon film having large-diameter grains (large-grain polycrystalline silicon film) produces the following new problems.
In general, the large-grain polycrystalline silicon film is formed by re-crystallization of an amorphous silicon film. However, in the recrystallization method, a single crystal is formed in the depth direction of the film, so that individual crystal planes differ in orientation (crystal axes), as shown in FIG. 24.
When impurity ions are doped by ion implantation into the gate electrode (large-grain polycrystalline silicon film) constituted of grains whose planes different in orientation, the depths of the doped impurity ions varies since a channeling rate differs depending upon the crystal plane orientation. If the depth of impurity ions differs, the threshold voltage of a MOSFET varies.
In addition, as a result that a channeling rate differs depending upon the plane orientation, the impurity ions doped into the gate electrode sometimes reach the silicon substrate. In this case, the threshold voltage of the MOSFET is extremely decreased.
Incidentally, as the gate electrode made of silicon, a dual-layered structure is known (H. Ito et al., xe2x80x9cGate electrode microstructure having stacked large-grain poly-Si with ultra-thin SiOx interlayer for Reliability in Sub-micro meter CMOSxe2x80x9d, IEDM 97, p635-638).
In this case, the gate electrode is obtained by forming a polycrystalline silicon film having large-diameter grains (large-grain polycrystalline silicon film), a thin insulating film (e.g., a thin oxide film such as native oxide film), and a polycrystalline silicon film having small diameter grains (small-grain polycrystalline silicon film) on the gate insulating film in sequential order.
The reason why the small-grain polycrystalline silicon film is formed on the large-grain polycrystalline silicon film with the thin insulating film interposed therebetween is to prevent the small grain polycrystalline silicon film from being formed under the influence of the crystallinity of the underlying small grain polycrystalline silicon film.
The present inventors consider that the MOSFET employing a conventional double-layered gate electrode has the following problems. The double-layered gate electrode has a thin insulating film between the large-grain polycrystalline silicon film and the small-grain polycrystalline silicon film functions as a resistant component. Therefore, the high frequency property of the MOSFET using the double layered gate electrode is degraded.
Furthermore, such a MOSFET has processing problems as set forth below. The double-layered gate electrode is formed by sequentially forming the large-grain polycrystalline silicon film, a thin insulating film, and thereafter, the small-grain polycrystalline silicon film and etching them in a retrograde order.
In this case, first, the etching between large and small grain poly-Si film in the published pager conditions for the thin insulating film are equal to the etching conditions for the gate oxide film. Second, the film thickness of the large-grain polycrystalline silicon film and the small-grain polycrystalline silicon film is reduced as the miniaturization of a device. Third, etching conditions for such a thin large-grain polycrystalline silicon film and the small-grain polycrystalline silicon film are not sufficiently controlled by present techniques. For these three reasons, the silicon substrate is also etched during the etching for the gate electrode formation process. As a result, parasitic resistance is increased and the characteristics of the MOSFET are degraded.
The present invention is attained to overcome the aforementioned conventional problems. An object of the present invention is to provide A MIS type semiconductor device and a method of manufacturing the MIS type semiconductor device which can suppress depletion of the gate electrode and channeling of impurity ions and simultaneously overcome degradation of the high frequency properties and problems associated with gate electrode processing time.
The MIS type semiconductor device according to the present invention comprises
a semiconductor substrate;
a gate insulating film formed on the semiconductor substrate; and
a gate electrode formed on the gate insulating film and formed of a polycrystalline silicon film.
The grains of a lower portion of the polycrystalline silicon film are larger in average diameter than the grain of an upper portion thereof. There is no peak in oxygen concentration in the film thickness direction in the polycrystalline silicon film.
According to the present invention, the lower portion of the polycrystalline silicon film is formed of the large-grain polycrystalline silicon. It is therefore possible to suppress fluctuation in threshold voltage caused by channeling during ion implantation. Furthermore, the upper portion of the polycrystalline silicon film is formed of the small-grain polycrystalline silicon. It is therefore possible to suppress depletion of the gate electrode caused by segregation/inactivation of the impurity ions in the grain boundary.
There is no peak in oxygen concentration in the polycrystalline silicon film. In other words, no oxide film is present in the region in which grain diameter of the polycrystalline silicon changes. It is therefore possible to overcome deterioration in high frequency properties and difficulty in etching during the gate electrode processing.
The average diameter of the polycrystalline silicon grains is obtained by dividing the length of a cross line, which is formed between a plane in parallel to the substrate and a plane in perpendicular to the substrate, by the number of the grain boundaries present on the cross line.
In another MIS-type semiconductor device according to the present invention comprises
a semiconductor substrate;
a gate insulating film formed on the semiconductor substrate; and
a gate electrode formed on the gate insulating film and formed of a polycrystalline silicon film,
in which a lower portion of the polycrystalline silicon film has larger grains in average diameter than an upper portion thereof; and a region in which the average grain diameter of the polycrystalline silicon film changes is set at a distance of 1 nm apart from an interface between the gate electrode and the gate insulating film.
According to the present invention, a region in which the average grain diameter of the polycrystalline silicon film changes is set at a distance of 1 nm apart from an interface between the gate electrode and the gate insulating film. It is therefore possible to effectively suppress depletion of the gate electrode. We will further describe with respect to this point in detail in embodiments.
In still another MIS-type semiconductor device according to the present invention comprises
a semiconductor substrate;
a gate insulating film formed on the semiconductor substrate;
a gate electrode formed on the gate insulating film and formed of a polycrystalline silicon film; and
two source/drain regions formed in a surface of the semiconductor substrate so as to sandwich the gate electrode,
in which a lower portion of the polycrystalline silicon film has larger grains in average diameter than an upper portion thereof, and a distance between a portion of the polycrystalline silicon film, at which the average grain diameter is changed, and an upper surface of the polycrystalline silicon film, is larger than a distance between a portion of the source drain regions having a peak impurity concentration and a surface of the semiconductor substrate.
According to the present invention, a distance between a interface in the polycrystalline silicon film, at which the average grain diameter is changed, and an upper surface of the polycrystalline silicon film, is larger than a depth of a peak impurity concentration of source/drain region measured from surface of the semiconductor substrate. It is therefore possible to efficiently suppress a problem of channeling of impurity. We will further describe this point in embodiments.
A method of manufacturing a semiconductor device according to the present invention comprises the steps of:
forming a gate insulating film on a semiconductor substrate;
forming a polycrystalline silicon film on the gate insulating film without exposing the semiconductor substrate to an air while film formation conditions are changed between a first half step and a latter half step of a film formation process; and
forming a gate electrode by processing the polycrystalline silicon film.
According to the present invention, the film formation process is changed between a first half process and a latter half process without exposing a semiconductor substrate to the air. It is therefore possible to form a polycrystalline silicon film, a lower portion of which has grains larger in average diameter than that of an upper portion, and which has no peak in oxygen concentration in a film-depth direction. We will describe as to this point in embodiments.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.